How to do post-synthesis simulation in ModelSim?

Hello Dave, I wonder whether you have relevant experience using counter to create clock signals, if you do, could you help me about the following question:

Now I am working on a design which needs different rate clock signals. However, some clock signals can not be achieved directly through PLL in the chip. So I plan to use counter and PLL to achieve the demanded clock signals.

As I know, if I use counter to create a clock signals, there may be some problems. Because the counter output can not guarantee that the counter output signals arrive at different components clock pins at exactly same time, these little time differences in signals arrive may cause serious problem that make the system does not work as expect. I just heard there is a IP core that like global clock, the input is the clock signals like the counter output, the outputs are still clock signals, however the output signals from the global clock can guarantee arriving different components at the exact time to avoid mismatch.

I try to find this IP core in QuartusII but I can't got it. I just wonder who have heard this type IP or used this before? if there is no IP core like I described, how can I handle the issue I describe above about using counter to generate the clock signals?

Thanks very much!