Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

How to do post-synthesis simulation in ModelSim?

I only know how to do RTL functional simulation (only need HDL files) and GTL timing simulation (need .vo or .vho and .sdo files)in ModelSim. However, how can I do post-synthesis simulation in Model...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

--- Quote Start ---

But how can I check how much clock routing resources I have used for the design in my FPGA chip?

--- Quote End ---

You don't. Quartus will tell you if it runs out. I'm sure there is a report file somewhere that you can look in, but in reality, you do not care. If your design synthesizes and passes timing, then you can test it.

Cheers,

Dave