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Now I am working on a design which needs different rate clock signals. However, some clock signals can not be achieved directly through PLL in the chip. So I plan to use counter and PLL to achieve the demanded clock signals.
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There's two ways to achieve what you want:
1) Use a higher clock rate and an enable signal.
If I have a component that needs to operate at 5MHz, then rather than creating a 5MHz clock, I create a 5MHz enable pulse, and clock at whatever the rest of my design operates at.
Why do it this way? Well, older generations of FPGAs had very limited clock routing, so this was your only option.
2) Use a counter to generate a clock.
This can work, up until the point that you use all the clock routing resources on your FPGA (if you create too many generated clocks).
You use TimeQuest to constrain this type of clock using the create_generated_clock .SDC command.
http://www.altera.com/support/software/timequest/clock/tq-generate-clock.html Since your generated clock will have a delay relative to the original, you should use clock domain crossing logic between your fast and slow clock domains.
My recommendation would be to use (2) wisely, in that you should try to group all 'slow' devices into one clock domain, and generate a single slow clock, rather than lots. If you were creating a Qsys system, then you would put all of these devices on the other side of a clock-crossing bridge.
Cheers,
Dave
Honored Contributor
