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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to constraint input & output clock of PLL

I'm using TimeQuest to constraint my project, but after FULL compilation, the TimeQuest report that setup violations exist between input & output clock of PLL？

Please see the detail below:

Info: Path# 1: Setup slack is -1.545 (VIOLATED)

Info: ===================================================================

Info: From Node : FreqMeasure_NiosII:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done

Info: To Node : FreqMeasure_NiosII:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1

Info: Launch Clock : clk

Info: Latch Clock : FreqMeasure_NiosII:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk1

Info:

Info: Data Arrival Path:

Info:

Info: Total (ns) Incr (ns) Type Element

Info: ========== ========= == ==== ===================================

Info: 60.000 60.000 launch edge time

Info: 63.301 3.301 R clock network delay

Info: 63.605 0.304 uTco FreqMeasure_NiosII:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done

Info: 63.605 0.000 RR CELL inst|the_clock_0|master_FSM|internal_master_read_done|regout

Info: 64.038 0.433 RR IC inst|the_clock_0|clock_0_master_read_done_sync|data_in_d1~feeder|datad

Info: 64.244 0.206 RR CELL inst|the_clock_0|clock_0_master_read_done_sync|data_in_d1~feeder|combout

Info: 64.244 0.000 RR IC inst|the_clock_0|clock_0_master_read_done_sync|data_in_d1|datain

Info: 64.352 0.108 RR CELL FreqMeasure_NiosII:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1

Info:

Info: Data Required Path:

Info:

Info: Total (ns) Incr (ns) Type Element

Info: ========== ========= == ==== ===================================

Info: 62.500 62.500 latch edge time

Info: 62.767 0.267 R clock network delay

Info: 62.807 0.040 uTsu FreqMeasure_NiosII:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1

Info:

Info: Data Arrival Time : 64.352

Info: Data Required Time : 62.807

Info: Slack : -1.545 (VIOLATED)

Info: ===================================================================

Info:

How to constraint input & output clock of PLL?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    - You have two clock assignments:

    - On the input port clk, probably done with a create_clock assignment

    - On the clk1 output of the PLL, done with a create_generated_clock, probably via derived_pll_clocks

    The setup requirement between these two is 2.5ns based on their clocking schemes. My guess is that the PLL does a phase shift, which is what causes the tight requirement.

    Bottom line is that this is probably the most restrictive setup requirement, and therefore what TimeQuest goes with by default. There are different ways to approach it:

    1) Do you think this setup requirement is incorrect? (Unlikely, I've never seen TQ make a mistage like this, and it is based purely on the clock assignments mentioned above.)

    2) Is it correctly using the most restrictive, but you want a looser requirement? You can add a multicycle assignment between the clocks to achieve this.

    3) Is there something wrong with the design? In general, you don't want registers connected where one is fed by the non-PLL clock and the other is fed by the PLL clock. Most likely everything should be fed after the PLL, and the design should be modified.

    4) The path is correct, but it's static or something, and you don't want it analyzed at all. A set_false_path assignment between the register or clocks would cut the timing from being analyzed.

    There may be other situations, but that's probably the bulk. The key is to understanding why TimeQuest is analyzing the path, how it should be analyzed, and determine where the disconnect is.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Thanks very much for you detailed info.

    My system is SOPC Builder system, the critical path listed above seem to be a path inside crossing clock bridge that generated automatically by SOPC Builder.

    I think I should set_false_path between input & output clock of PLL, am I right?
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I can't say for sure, as it's really a design dependent issue(does this path need to transfer synchronously or not.) If it's on different sides of the clock bridge(which I believe is a hand-shaking transfer that doesn't need to be timed), then yes, they can probably be cut. Looking at the source register:

    clock_ 0_master_FSM:master_FSM|internal_master_read_done

    and the destination register names:

    clock_ 0_master_read_done_sync_module:clock_0_master_read _done_sync|data_in_d1

    I'm guessing it's part of this too, based on the sync name. But this is just a guess based on what you've described. If you're sure you've put the separate clocks on different sides of a module that is supposed to handle asynchronous clocks, than yes, it can be cut.