How to constraint input & output clock of PLL

- You have two clock assignments:

- On the input port clk, probably done with a create_clock assignment

- On the clk1 output of the PLL, done with a create_generated_clock, probably via derived_pll_clocks

The setup requirement between these two is 2.5ns based on their clocking schemes. My guess is that the PLL does a phase shift, which is what causes the tight requirement.

Bottom line is that this is probably the most restrictive setup requirement, and therefore what TimeQuest goes with by default. There are different ways to approach it:

1) Do you think this setup requirement is incorrect? (Unlikely, I've never seen TQ make a mistage like this, and it is based purely on the clock assignments mentioned above.)

2) Is it correctly using the most restrictive, but you want a looser requirement? You can add a multicycle assignment between the clocks to achieve this.

3) Is there something wrong with the design? In general, you don't want registers connected where one is fed by the non-PLL clock and the other is fed by the PLL clock. Most likely everything should be fed after the PLL, and the design should be modified.

4) The path is correct, but it's static or something, and you don't want it analyzed at all. A set_false_path assignment between the register or clocks would cut the timing from being analyzed.

There may be other situations, but that's probably the bulk. The key is to understanding why TimeQuest is analyzing the path, how it should be analyzed, and determine where the disconnect is.