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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to constraint input & output clock of PLL

I'm using TimeQuest to constraint my project, but after FULL compilation, the TimeQuest report that setup violations exist between input & output clock of PLL？ Please see the detail below: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks very much for you detailed info.

My system is SOPC Builder system, the critical path listed above seem to be a path inside crossing clock bridge that generated automatically by SOPC Builder.

I think I should set_false_path between input & output clock of PLL, am I right?