How to constraint input & output clock of PLL

I can't say for sure, as it's really a design dependent issue(does this path need to transfer synchronously or not.) If it's on different sides of the clock bridge(which I believe is a hand-shaking transfer that doesn't need to be timed), then yes, they can probably be cut. Looking at the source register:

clock_ 0_master_FSM:master_FSM|internal_master_read_done

and the destination register names:

clock_ 0_master_read_done_sync_module:clock_0_master_read _done_sync|data_in_d1

I'm guessing it's part of this too, based on the sync name. But this is just a guess based on what you've described. If you're sure you've put the separate clocks on different sides of a module that is supposed to handle asynchronous clocks, than yes, it can be cut.