How to connect my FIFO to mSGDMA inside Qsys?

Hi Jerry,

you are trying to write to an output. The dma_write_master is designed to write streaming Data into a memory. For example your Host-RAM. But you connected its Memory Mapped Master to the Output-Port of fifo_0. I don't know exactly how you want to design this, but I think you want this:

[outside logic] ---> [MM or ST IN ---> FIFO ---> ST OUT] ---> [ST IN ---> DMA_WRITE_MASTER ---> MM OUT] ---> [MM IN (txs) ---> PCIE_HIP ---> RX/TX_OUT] ---> [Your Host]

Also connect the CSR-Registers directly to one of your PCIe-BARs. You can read and write them via DMA, but it does not make sense because a direct access will be much faster. Use DMA only for "large" data access.

Try this.

Do you need to write data from your host to your FPGA? If not, remove the dma_read_master.

Another very good idea:

If you edit the Verilog-Code of the dma_write_master, you can route out the fill level of its data-fifo. By this way you can throw away any other fifo and work directly with the fifos of the write_master.

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Hi Jerry,

you are trying to write to an output. The dma_write_master is designed to write streaming Data into a memory. For example your Host-RAM. But you connected its Memory Mapped Master to the Output-Port of fifo_0. I don't know exactly how you want to design this, but I think you want this:

[outside logic] ---> [MM or ST IN ---> FIFO ---> ST OUT] ---> [ST IN ---> DMA_WRITE_MASTER ---> MM OUT] ---> [MM IN (txs) ---> PCIE_HIP ---> RX/TX_OUT] ---> [Your Host]

Also connect the CSR-Registers directly to one of your PCIe-BARs. You can read and write them via DMA, but it does not make sense because a direct access will be much faster. Use DMA only for "large" data access.

Try this.

Do you need to write data from your host to your FPGA? If not, remove the dma_read_master.

Another very good idea:

If you edit the Verilog-Code of the dma_write_master, you can route out the fill level of its data-fifo. By this way you can throw away any other fifo and work directly with the fifos of the write_master.

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Hi Steffen,

Yes, i need put my data from my logic to my host, and receive a little data which is of configuration for my system from my host. I'll change it according you advised.

--- Quote Start ---

Hi Jerry,

you are trying to write to an output. The dma_write_master is designed to write streaming Data into a memory. For example your Host-RAM. But you connected its Memory Mapped Master to the Output-Port of fifo_0. I don't know exactly how you want to design this, but I think you want this:

[outside logic] ---> [MM or ST IN ---> FIFO ---> ST OUT] ---> [ST IN ---> DMA_WRITE_MASTER ---> MM OUT] ---> [MM IN (txs) ---> PCIE_HIP ---> RX/TX_OUT] ---> [Your Host]

Also connect the CSR-Registers directly to one of your PCIe-BARs. You can read and write them via DMA, but it does not make sense because a direct access will be much faster. Use DMA only for "large" data access.

Try this.

Do you need to write data from your host to your FPGA? If not, remove the dma_read_master.

Another very good idea:

If you edit the Verilog-Code of the dma_write_master, you can route out the fill level of its data-fifo. By this way you can throw away any other fifo and work directly with the fifos of the write_master.

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Hi Steffen,

I read your comments carefully, do you mean if i want put my data to Qsys, i should connect the FIFO-out to DMA write master? Can't connect it to DMA read master? But, when connect FIFO's ST out to DMA write master, qsys will report me one error:"The source has 256 bits per symbol, while the sink has 8" as attached shows.

Hi Jerry,

sorry for the late answer.

The Write-Master writes to your Host-Memory. It reads from your Fifo.

The Read-Master reades from your Host-Memory. It writes to a (whatever) Data Sink.

This is, why you have to connect the Output of your Fifo (Streaming source) to the Write-Master (Streaming sink).

When you have a mismatch in data-width of write-master and fifo, you should correct this by editing the parameters of those cores.

If you want to use a 256Bit fifo, you should also configure the write-master with a 256Bit fifo. At the moment the write-master fifo is 8Bit.

Of course QSYS gives you this mismatch error.

Just double click the write master and configure the data fifo to 256Bit.

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Hi Jerry,

sorry for the late answer.

The Write-Master writes to your Host-Memory. It reads from your Fifo.

The Read-Master reades from your Host-Memory. It writes to a (whatever) Data Sink.

This is, why you have to connect the Output of your Fifo (Streaming source) to the Write-Master (Streaming sink).

When you have a mismatch in data-width of write-master and fifo, you should correct this by editing the parameters of those cores.

If you want to use a 256Bit fifo, you should also configure the write-master with a 256Bit fifo. At the moment the write-master fifo is 8Bit.

Of course QSYS gives you this mismatch error.

Just double click the write master and configure the data fifo to 256Bit.

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Hi Steffen,

Thanks for you reply, it's clear now for me, and i know how to expose ports and connect inside Qsys. However, as attached file shows, the DMA write-master(ST sink) data width is already 256-bits.

Hmmmmmm, this is really odd.OK, your Write-Master has the correct width.

Did you download the newest msgdma from Altera-Wiki? Perhaps this is a Bug.

I also don't know, what's the matter. Perhaps you should contact BadOmen with this issue.

I didn't read the entire thread but sounds like you want to expose the write master streaming port to logic outside of Qsys. You can do that by clicking on the write master data streaming port twice in the export column and it should allow you to assign a name to this port which will show up at the top level of the Qsys system.

The issue mentioned at the top sounds a either a mismatch in data widths or a mismatch with symbol widths. The mSGDMA deals with symbols of 8-bit since the symbols have to land in byte lanes in memory after the symbols get reversed. So if you had a 32-bit write master and the streaming data comes in as D[31:0] = 32'hDEADBEEF you will see the symbols get reversed and written as 32'hEFBEADDE out to memory. Avalon-MM uses little endian byte ordering while Avalon-ST uses network order (a.k.a. big endian) so that's why the symbols get shuffled around internally. If you are connecting a FIFO with a different symbol size I would just create a little gasket that has an Avalon-ST source and sync pair with the source using 8-bit symbols and the sink using whatever your FIFO uses as a symbol size to adapt between the symbol sizes. This gasket is just wires so you are simply tricking Qsys into letting you integrate these blocks together.

I have been keeping the mSGDMA up to date on the wiki but I recommend using the cores that appear in Qsys starting in 14.0.

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I didn't read the entire thread but sounds like you want to expose the write master streaming port to logic outside of Qsys. You can do that by clicking on the write master data streaming port twice in the export column and it should allow you to assign a name to this port which will show up at the top level of the Qsys system.

The issue mentioned at the top sounds a either a mismatch in data widths or a mismatch with symbol widths. The mSGDMA deals with symbols of 8-bit since the symbols have to land in byte lanes in memory after the symbols get reversed. So if you had a 32-bit write master and the streaming data comes in as D[31:0] = 32'hDEADBEEF you will see the symbols get reversed and written as 32'hEFBEADDE out to memory. Avalon-MM uses little endian byte ordering while Avalon-ST uses network order (a.k.a. big endian) so that's why the symbols get shuffled around internally. If you are connecting a FIFO with a different symbol size I would just create a little gasket that has an Avalon-ST source and sync pair with the source using 8-bit symbols and the sink using whatever your FIFO uses as a symbol size to adapt between the symbol sizes. This gasket is just wires so you are simply tricking Qsys into letting you integrate these blocks together.

I have been keeping the mSGDMA up to date on the wiki but I recommend using the cores that appear in Qsys starting in 14.0.

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Hi BadOmen&Steffen,

I changed the DC-FIFO's parameter settings, and that error was killed, the settings now is as below:

http://www.alteraforum.com/forum/attachment.php?attachmentid=9887&stc=1

Now the data width still 256-bit. I just change the "Symbols per beat" from default value 1 to 32, and change the "Bits per symbol" to 8 (32*8=256). It seems the DCFIFO can be connected to the SGDMA write-master now.

The next step for me is to learn how to control the FIFO's exported "in" port and write data into it from my user logic.

Thanks for you guys help to me!!!

One more question:

Can an Avalon-mm master connect to an avalon-slave with different width? For example, a 256-bit master connects to a 128-bit slave.

Yes, QSYS will automatically insert a MM-Bridge. But this is not very efficient.

An example:

You want to connect ten PIOs with 32Bit width to your PCIe, QSYS will create ten Bridges between PCIe and the PIOs.

This will need many ressources on your FPGA.

The Better way:

Implement one MM-Bridge by yourself and connect all ten PIOs to the Bridge and the other Port to PCIe. By this way you safe the Ressources for nine Bridges.