--- Quote Start ---
Hi Jerry,
you are trying to write to an output. The dma_write_master is designed to write streaming Data into a memory. For example your Host-RAM. But you connected its Memory Mapped Master to the Output-Port of fifo_0. I don't know exactly how you want to design this, but I think you want this:
[outside logic] ---> [MM or ST IN ---> FIFO ---> ST OUT] ---> [ST IN ---> DMA_WRITE_MASTER ---> MM OUT] ---> [MM IN (txs) ---> PCIE_HIP ---> RX/TX_OUT] ---> [Your Host]
Also connect the CSR-Registers directly to one of your PCIe-BARs. You can read and write them via DMA, but it does not make sense because a direct access will be much faster. Use DMA only for "large" data access.
Try this.
Do you need to write data from your host to your FPGA? If not, remove the dma_read_master.
Another very good idea:
If you edit the Verilog-Code of the dma_write_master, you can route out the fill level of its data-fifo. By this way you can throw away any other fifo and work directly with the fifos of the write_master.
--- Quote End ---
Hi Steffen,
I read your comments carefully, do you mean if i want put my data to Qsys, i should connect the FIFO-out to DMA write master? Can't connect it to DMA read master? But, when connect FIFO's ST out to DMA write master, qsys will report me one error:"The source has 256 bits per symbol, while the sink has 8" as attached shows.
Honored Contributor
