How to connect my FIFO to mSGDMA inside Qsys?

I didn't read the entire thread but sounds like you want to expose the write master streaming port to logic outside of Qsys. You can do that by clicking on the write master data streaming port twice in the export column and it should allow you to assign a name to this port which will show up at the top level of the Qsys system.

The issue mentioned at the top sounds a either a mismatch in data widths or a mismatch with symbol widths. The mSGDMA deals with symbols of 8-bit since the symbols have to land in byte lanes in memory after the symbols get reversed. So if you had a 32-bit write master and the streaming data comes in as D[31:0] = 32'hDEADBEEF you will see the symbols get reversed and written as 32'hEFBEADDE out to memory. Avalon-MM uses little endian byte ordering while Avalon-ST uses network order (a.k.a. big endian) so that's why the symbols get shuffled around internally. If you are connecting a FIFO with a different symbol size I would just create a little gasket that has an Avalon-ST source and sync pair with the source using 8-bit symbols and the sink using whatever your FIFO uses as a symbol size to adapt between the symbol sizes. This gasket is just wires so you are simply tricking Qsys into letting you integrate these blocks together.

I have been keeping the mSGDMA up to date on the wiki but I recommend using the cores that appear in Qsys starting in 14.0.