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Hi Jerry,
sorry for the late answer.
The Write-Master writes to your Host-Memory. It reads from your Fifo.
The Read-Master reades from your Host-Memory. It writes to a (whatever) Data Sink.
This is, why you have to connect the Output of your Fifo (Streaming source) to the Write-Master (Streaming sink).
When you have a mismatch in data-width of write-master and fifo, you should correct this by editing the parameters of those cores.
If you want to use a 256Bit fifo, you should also configure the write-master with a 256Bit fifo. At the moment the write-master fifo is 8Bit.
Of course QSYS gives you this mismatch error.
Just double click the write master and configure the data fifo to 256Bit.
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Hi Steffen,
Thanks for you reply, it's clear now for me, and i know how to expose ports and connect inside Qsys. However, as attached file shows, the DMA write-master(ST sink) data width is already 256-bits.
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