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Altera_Forum's avatar
Altera_Forum
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10 years ago

How do I infer dffe instead of mux

Hi,

I am having a problem getting quartus to synthesize part of my design as a dffe register when the output of the register is fed to another module.

If I run the following code (without a sub-module) through analysis & synthesis, and then view the results in the RTL viewer, the result is a dffe as expect: 

module dffe_test
(
  input wire        clk,
  input wire        ctrl,
  input wire   dat,
  output wire       result
);
reg  dat_r;
  always @ ( posedge clk )
  begin
    if ( ctrl )
      begin
        dat_r <= dat;
      end
  end
assign result = { &dat_r };
endmodule

However, the following code uses muxes and a dff is less efficient: 


module dffe_test
(
  input wire        clk,
  input wire        ctrl,
  input wire   dat,
  output wire       result
);
reg  dat_r;
  always @ ( posedge clk )
  begin
    if ( ctrl )
      begin
        dat_r <= dat;
      end
  end
  widget widget_inst
  (
    .clk   ( clk ),
    .dat   ( { dat_r } ),
    .result( result )
  );
endmodule

I have attached a screenshot of the TRL viewer output for both examples.

How do I get the second example to use a dffe for register dat_r ?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Widget is just an and gate: 

    module widget
(
  input wire      clk,
  input wire dat,
  output wire     result
);
assign result = { &dat };
endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    It's just the RTL viewer being less than brilliant. You basically should be inferring a clock enable - from the if statement, but sometimes the RTL viewer misses this is instead draws a mux to make the clock enable. In reality due to the way logic blocks are structured it probably wouldn't make any performance difference, and when the fitter runs it will probably optimise to a clock enable.

    A better thing to look at would be the technology viewer, that will show how it is actually implemented.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks tcworld, you are right, the technology map viewer does show that is has not used any muxes.

    https://www.alteraforum.com/forum/attachment.php?attachmentid=10890

    But in a complex design it is not very human readable. :-(

    I recently taught myself Verilog after many years of using schematic entry, so I have been using the RLT viewer to check my coding to ensure it produced an efficient design.

    But then I wasn’t seeing what I expected and thought my coding was at fault.

    Thanks for your help.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    To make it most readable, you can create a module for a D-Flip-Flop which has clock, data, enable, and reset inputs. Then just use this module in place of the always block. In the RTL viewer you will then see it as a box. You can also add parameters to control the width of the data and output signals which would make it useful for wide buses as well as single bits.

    As the designs get larger and more complicated, the RTL viewer starts to be less and less helpful (it's good for some things, but other stuff gets obfuscated).