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Honored Contributor
Honored ContributorHow do I infer dffe instead of mux
Hi, I am having a problem getting quartus to synthesize part of my design as a dffe register when the output of the register is fed to another module. If I run the following code (without a su...
Altera_ForumHonored Contributor
Honored ContributorWidget is just an and gate:
module widget
(
input wire clk,
input wire dat,
output wire result
);
assign result = { &dat };
endmodule
