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Honored Contributor
Honored ContributorHow do I infer dffe instead of mux
Hi, I am having a problem getting quartus to synthesize part of my design as a dffe register when the output of the register is fed to another module. If I run the following code (without a su...
Altera_ForumHonored Contributor
Honored ContributorIt's just the RTL viewer being less than brilliant. You basically should be inferring a clock enable - from the if statement, but sometimes the RTL viewer misses this is instead draws a mux to make the clock enable. In reality due to the way logic blocks are structured it probably wouldn't make any performance difference, and when the fitter runs it will probably optimise to a clock enable.
A better thing to look at would be the technology viewer, that will show how it is actually implemented.
