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Honored Contributor
Honored ContributorHow do I infer dffe instead of mux
Hi, I am having a problem getting quartus to synthesize part of my design as a dffe register when the output of the register is fed to another module. If I run the following code (without a su...
Altera_ForumHonored Contributor
Honored ContributorTo make it most readable, you can create a module for a D-Flip-Flop which has clock, data, enable, and reset inputs. Then just use this module in place of the always block. In the RTL viewer you will then see it as a box. You can also add parameters to control the width of the data and output signals which would make it useful for wide buses as well as single bits.
As the designs get larger and more complicated, the RTL viewer starts to be less and less helpful (it's good for some things, but other stuff gets obfuscated).
