How do I infer dffe instead of mux

Thanks tcworld, you are right, the technology map viewer does show that is has not used any muxes.

https://www.alteraforum.com/forum/attachment.php?attachmentid=10890

But in a complex design it is not very human readable. :-(

I recently taught myself Verilog after many years of using schematic entry, so I have been using the RLT viewer to check my coding to ensure it produced an efficient design.

But then I wasn’t seeing what I expected and thought my coding was at fault.

Thanks for your help.