How connect my data to pcie interafce in Qsys?

Possibly the easiest approach would be to add a dual-port FIFO within your Qsys system and to export the write-side Avalon-MM Slave port so that the wires appear in your Qsys top level module. Then, hook your external logic to those wires to push the data into the Qsys FIFO. You can also do things like add PIO components to control your external logic, if needed.

Alternatively, wrap your existing logic into a Qsys custom component and add an Avalon-MM Slave port to provide access to your existing FIFO, or possibly control/status registers for your custom logic.

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Possibly the easiest approach would be to add a dual-port FIFO within your Qsys system and to export the write-side Avalon-MM Slave port so that the wires appear in your Qsys top level module. Then, hook your external logic to those wires to push the data into the Qsys FIFO. You can also do things like add PIO components to control your external logic, if needed.

Alternatively, wrap your existing logic into a Qsys custom component and add an Avalon-MM Slave port to provide access to your existing FIFO, or possibly control/status registers for your custom logic.

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Hi ted:

Thanks for you reply!

I have another question need you help. It seems the first way is easy for me currently. connect the dual-port fifo read-side to dma? do i need to prepare any fifo-reading logic or the dma can read data from fifo automatically?

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I have another question need you help. It seems the first way is easy for me currently. connect the dual-port fifo read-side to dma? do i need to prepare any fifo-reading logic or the dma can read data from fifo automatically?

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You would instantiate the On-Chip FIFO component within Qsys and connect it's 'out' Avalon-MM slave to the DMA read Avalon-MM Master port, the same way you have it connected to vanilla On-Chip Memory in your existing system.

Then, export the 'in' Avalon-MM Slave and glue your logic to the 'write' and 'writedata' signals at the toplevel.

You do not need to create any further logic (HDL) to allow the DMA to read from the FIFO. However, you do need software etc. to command the DMA to perform that read transaction at that address of your FIFO.

This similar thread from yesterday has a similar use of the FIFO (substituting NIOS and PCIe):

http://www.alteraforum.com/forum/showthread.php?t=42535

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You would instantiate the On-Chip FIFO component within Qsys and connect it's 'out' Avalon-MM slave to the DMA read Avalon-MM Master port, the same way you have it connected to vanilla On-Chip Memory in your existing system.Then, export the 'in' Avalon-MM Slave and glue your logic to the 'write' and 'writedata' signals at the toplevel.You do not need to create any further logic (HDL) to allow the DMA to read from the FIFO. However, you do need software etc. to command the DMA to perform that read transaction at that address of your FIFO.This similar thread from yesterday has a similar use of the FIFO (substituting NIOS and PCIe):http://www.alteraforum.com/forum/showthread.php?t=42535

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Hi Ted:As my first post shown, this ref design doesn't use soft core (nios). Any my question is how to start dma tranfering after i input data into the fifo?

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Hi Ted:As my first post shown, this ref design doesn't use soft core (nios). Any my question is how to start dma tranfering after i input data into the fifo?

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It's just another memory location, except you would need to program for a non-incrementing read since it's a FIFO. Other than that there is really no difference from continuing to do what you have already been doing in the past in order to access the other memories in your system.

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It's just another memory location, except you would need to program for a non-incrementing read since it's a FIFO. Other than that there is really no difference from continuing to do what you have already been doing in the past in order to access the other memories in your system.

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Hi ted,

Thanks for you patience!

Because i'm a newer of pcie application, i just don't know how pcie ip/hard ip to initialize the dma? i'm not clear about the procedure of the data transform between fpga and pc host thru pcie link.

I would suggest working through an existing design example and understanding everything that it is doing, before worrying about adding your own custom parts to your hardware.

Here is one such example:

http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs

If you study the source code, you will see where the DMA in the FPGA is being controlled by software executing on the PC.

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I would suggest working through an existing design example and understanding everything that it is doing, before worrying about adding your own custom parts to your hardware.

Here is one such example:

http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs

If you study the source code, you will see where the DMA in the FPGA is being controlled by software executing on the PC.

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hi ted,

Actually, all of my questions were coming from this example, >0<! Maybe, i need involve deeply into this example! I will discuss with you after i understand this project clearly! Thanks again!

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hi ted,

Actually, all of my questions were coming from this example, >0<! Maybe, i need involve deeply into this example! I will discuss with you after i understand this project clearly! Thanks again!

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Hello Jerry,

Now I hope you alreadu found out what to do. I am stuck now at the same point: I have a QSys Pcie and my logic which I dont know how to integrate. I need to read data coming to memory then make calculations and then send it back to Memory and so on streaming fasion.

Please help my how to start then what you recommend