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I have another question need you help. It seems the first way is easy for me currently. connect the dual-port fifo read-side to dma? do i need to prepare any fifo-reading logic or the dma can read data from fifo automatically?
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You would instantiate the On-Chip FIFO component within Qsys and connect it's 'out' Avalon-MM slave to the DMA read Avalon-MM Master port, the same way you have it connected to vanilla On-Chip Memory in your existing system.
Then, export the 'in' Avalon-MM Slave and glue your logic to the 'write' and 'writedata' signals at the toplevel.
You do not need to create any further logic (HDL) to allow the DMA to read from the FIFO. However, you do need software etc. to command the DMA to perform that read transaction at that address of your FIFO.
This similar thread from yesterday has a similar use of the FIFO (substituting NIOS and PCIe):
http://www.alteraforum.com/forum/showthread.php?t=42535
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