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You would instantiate the On-Chip FIFO component within Qsys and connect it's 'out' Avalon-MM slave to the DMA read Avalon-MM Master port, the same way you have it connected to vanilla On-Chip Memory in your existing system.Then, export the 'in' Avalon-MM Slave and glue your logic to the 'write' and 'writedata' signals at the toplevel.You do not need to create any further logic (HDL) to allow the DMA to read from the FIFO. However, you do need software etc. to command the DMA to perform that read transaction at that address of your FIFO.This similar thread from yesterday has a similar use of the FIFO (substituting NIOS and PCIe):
http://www.alteraforum.com/forum/showthread.php?t=42535 --- Quote End ---
Hi Ted:As my first post shown, this ref design doesn't use soft core (nios). Any my question is how to start dma tranfering after i input data into the fifo?
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