High-speed transmission interface at around 3 meters for FPGA to FPGA communication

I can't believe it. Even though I added lvds_en for frame synchronization in the interface,

it still completes the reception on the rising edge of the 11th lvds_clk.

Below are my Verilog code and output results. What might I have overlooked?

module lvds_receiver (
	input wire clk,
	input wire reset,

	input wire lvds_en,
	input wire lvds_clk,
	input wire lvds_data,
	output reg [11:0] data_out,

	output reg gpio_1,
	output reg gpio_2
);
	reg [1:0] state;
	reg lvds_clk_prev;
	reg [3:0] loop = 4'h0;
	reg [11:0] data_reg = 0;

	
	parameter IDLE = 2'b00;
	parameter RX = 2'b01;
	parameter DONE = 2'b10;


	// lvds_clk_rising_edge
	wire lvds_clk_rising_edge = !lvds_clk_prev && lvds_clk;
	
	always @(posedge clk or negedge reset) begin
	
		if(!reset) begin
			state <= IDLE;
		end
	
		case(state)
			IDLE: begin
				if(!lvds_en) begin
					loop <= 4'd0;
					state <= RX;
				end
			end
			
			RX: begin
				lvds_clk_prev <= lvds_clk;

				// Check for rising edge of lvds_clk
				if (lvds_clk_rising_edge) begin
					data_reg <= {data_reg[10:0], lvds_data};
					loop <= loop + 4'd1;
					gpio_2 <= ~gpio_2;
				end
				// When 12 bits are received, update data_out and reset loop
				if (loop == 12) begin
					gpio_1 <= ~gpio_1;
					state <= DONE;
				end
			end
			
			DONE: begin
				data_out <= data_reg;
				if(lvds_en) begin
					state <= IDLE;
				end
			end
//			default: state <= IDLE;		
		endcase
	end

endmodule