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Altera_Forum
Honored Contributor
Honored ContributorHelp needed in VHDL Testbench
Hi all,
I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the dir_s is incremented only for one value ie. when fmcw_ramp_o >= fmcw_bw_i and for all other values its zero. Because of this, Ì am getting this error "wrong output: addition should take place". I don't know how to solve this problem. I know for sure that dir_s should be 1 till it reaches the condition. I need to know how dir_s will be 1 continuously till fmcw_ramp_o< fstep_i or = "0000". The code looks like this:p_check_step: process(delayed_rst_s, clk_128meg_i)
begin
if (delayed_rst_s = '0') then
dir_s <= '0';
old_fmcw_ramp_s <= (others => '0');
elsif (clk_128meg_i'event and clk_128meg_i = '0') then
if (enable_i = '1' and fmcw_trig_i = '1') then
if( dir_s = '0') then
assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) + unsigned(fstep_i)) report " wrong output: addition should take place" severity error;
else
assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) - unsigned(fstep_i)) report " wrong output: subtraction should take place" severity error;
end if;
if (fmcw_ramp_o >= fmcw_bw_i) then
dir_s <= '1';
elsif (fmcw_ramp_o < fstep_i) then
dir_s <= '0';
elsif (fmcw_ramp_o = "000000000000000000000000") then
dir_s <= '0';
end if;
old_fmcw_ramp_s <= fmcw_ramp_o;
else
dir_s <= '0';
old_fmcw_ramp_s <= (others => '0');
end if;
end if;
end process;begin
if (reset_n_i = '0') then
temp_s <= 0;
cnt_s <= '0';
elsif (clk_128meg_i'event and clk_128meg_i = '1') then
if (enable_i = '1' and fmcw_trig_i = '1') then
if (temp_s <= to_integer(unsigned(fstep_i))) then
temp_s <= temp_s + to_integer(unsigned(fstep_i)); -- Accumulated values of temp_s and fstep_i
cnt_s <= '0';
elsif (temp_s = 0) then
temp_s <= temp_s - to_integer(unsigned(fstep_i));
cnt_s <= '0';
elsif (temp_s >= (to_integer(unsigned(fmcw_bw_i)))) then
temp_s <= temp_s - to_integer(unsigned(fstep_i));
cnt_s <= '1';
elsif (cnt_s = '0') then
temp_s <= temp_s + to_integer(unsigned(fstep_i)); -- Up counter
else
temp_s <= temp_s - to_integer(unsigned(fstep_i)); -- Down counter
end if;
else
temp_s <= 0;
cnt_s <= '0';
end if;
end if;
end process;36 Replies
Altera_Forum--- Quote Start --- std_logic_vector is not meant to represent arithmetic values, the types unsigned and signed are meant to do that. Unless you are using non-standard VHDL packages (like std_logic_unsigned/signed), if you are using std_logic_vector, then using >< or = will always fail if there is a missmatch in vector length. Instead of posting just a extract without the libraries for reference, it can be hard to understand the whole picture. Post the whole code so we can see the code in context. --- Quote End --- This is the entire testbench code
Now I have another problem. My code is not working for the input 16777215. its overflowing and i don't need to do that. Please help mep_stim: process begin wait for 10 ns; reset_n_i <= '1'; wait for 15 ns; enable_i <= '1'; fmcw_trig_i <= '1'; fmcw_bw_i <= "000000000000111000000000"; fstep_i <= "0011100000"; wait for 500 ns; fmcw_bw_i <= "001111111111111111111111"; -- 4194303 fstep_i <= "0011111111"; -- 255 wait for 1 ms; fmcw_bw_i <= "011111111111111111111111"; -- 8388607 fstep_i <= "0111111111"; -- 511 wait for 1 ms; fmcw_bw_i <= "111111111111111111111110"; -- 16777215 fstep_i <= "1111111110"; -- 1023 wait for 10 ms; reset_n_i <= '0'; wait for 1 ms; reset_n_i <= '1'; wait for 1 ms; enable_i <= '0'; fmcw_trig_i <= '0'; wait for 1 ms; enable_i <= '1'; fmcw_trig_i <= '1'; wait for 1 ms; assert false report "end of the simulation" severity failure; end process; delayed_rst_s <= reset_n_i after 1 ns; p_check_bw_rst: process(delayed_rst_s, clk_128meg_i) begin if (delayed_rst_s = '0') then assert fmcw_ramp_o = "000000000000000000000000" report "output not set to default value when reset_n_i=0" severity error; elsif (clk_128meg_i'event and clk_128meg_i = '0') then if (enable_i= '1' and fmcw_trig_i = '1') then assert fmcw_ramp_o < std_logic_vector(unsigned(fmcw_bw_i) + unsigned(fstep_i)) report "output value is larger than fmcw_bw_i" severity error; else assert fmcw_ramp_o = "000000000000000000000000" report "Output not set to default value when enable_i and fmcw_trig_i=0" severity error; end if; end if; end process; p_check_step: process(delayed_rst_s, clk_128meg_i) begin if (delayed_rst_s = '0') then dir_s <= '0'; old_fmcw_ramp_s <= (others => '0'); elsif (clk_128meg_i'event and clk_128meg_i = '0') then if (enable_i = '1' and fmcw_trig_i = '1') then if( dir_s = '1') then assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) - unsigned(fstep_i)) report " wrong output: subtraction should take place" severity error; else assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) + unsigned(fstep_i)) report " wrong output: addition should take place" severity error; end if; if (to_integer(unsigned(fmcw_ramp_o)) > to_integer(unsigned(fmcw_bw_i) - unsigned(fstep_i)))then dir_s <= '1'; elsif (to_integer(unsigned(fmcw_ramp_o)) <= to_integer(unsigned(fstep_i))) then dir_s <= '0'; end if; old_fmcw_ramp_s <= fmcw_ramp_o; else dir_s <= '0'; old_fmcw_ramp_s <= (others => '0'); end if; end if; end process;- Altera_Forum
I am in a real hurry
- Altera_Forum--- Quote Start --- I am in a real hurry --- Quote End --- Don't hurry, speed is dangerous! shouldn't "111111111111111111111110"; be "111111111111111111111111";
- Altera_Forum
I'm sorry, yes, I have misspelled it, I have changed fmcw_bw_i to 111111.... but still there is overflowing. Please help me out
- Altera_Forum--- Quote Start --- I'm sorry, yes, I have misspelled it, I have changed fmcw_bw_i to 111111.... but still there is overflowing. Please help me out --- Quote End --- and 1023 should be "111111111" addition/subtraction output must be 1 bit more than widest input
- Altera_Forum
Hello,
One basic question regarding the testbench. If we are not given the VHDL source code but only the components of the design and if we are asked to write a testbench code for its verification, should we need to use "port map" declaration. I assume its not, because we don't have any source file components to port map with. But I am not sure. Can anyone tell me if my assumption is correct or not. Thanks in advance - Altera_Forum
Yes, you can (and will need to ) write a port map. But you cannot run the simulation as there is nothing to bind the component to.
A component just tells the compiler about an entity interface. - Altera_Forum--- Quote Start --- Yes, you can (and will need to ) write a port map. But you cannot run the simulation as there is nothing to bind the component to. A component just tells the compiler about an entity interface. --- Quote End --- What if I need to run the simulation
- Altera_Forum
Then you need the source code, or a netlist.
- Altera_Forum
Hello,
I needed to design a glitch rejection module in VHDL and I have written the testbench accordingly only. I don't have the source module but I have the design which is as follows: http://www.alteraforum.com/forum/attachment.php?attachmentid=12702&stc=1 . Thetestbench is as follows:
First, old_phi_e_s should be updated with the phi_e_i only in the rising edge. I don't know how to do this?? What I need to do is , I need to check for the condition if (abs(signed(phi_e_i) - signed(old_phi_e_s)) >= to_integer(unsigned(new_thresh_s))) then, phi_e_gr_o = old_phi_e_s , else phi_e_gr_o = phi_e_i. But it is not doing so. I am getting the errors "Wrong output: phi_e_gr_o should be equal to old phi_e_i" and "Wrong output: phi_e_gr_o should be equal to phi_e_i". Please help me to solve this issue. Thanks in advance.stim_proc:process begin wait for 10 ns; reset_n_i <= '1'; wait for 15 ns; enable_i <= '1'; phi_e_i <= "101010101111010101101010101101010101"; thresh_i <= "11111111"; wait for 100 ns; phi_e_i <= "111010101101010101010101010101010101"; thresh_i <= "00010110"; wait for 1 ms; reset_n_i <= '0'; wait for 1 ms; reset_n_i <= '1'; wait for 1 ms; enable_i <= '0'; wait for 1 ms; enable_i <= '1'; wait for 1 ms; assert False report "End simulation!" severity Failure; end process; delay_rst_s <= reset_n_i after 1 ns; p_check_outp: process(delay_rst_s, clk_128meg_i) begin if (delay_rst_s = '0') then sel_s <= '0'; old_phi_e_s <= (others => '0'); assert phi_e_gr_o = "000000000000000000000000000000000000" report "Output not set to default value when reset_n_i= 0" severity error; elsif (clk_128meg_i'event and clk_128meg_i = '0')then if (enable_i = '1') then old_phi_e_s <= phi_e_i; new_thresh_s <= std_logic_vector("0000000000000000000000000000" & thresh_i); if (sel_s = '1') then assert phi_e_gr_o = old_phi_e_s report "Wrong output: phi_e_gr_o should be equal to old phi_e_i" severity error; elsif (sel_s = '0') then assert phi_e_gr_o = phi_e_i report "Wrong output: phi_e_gr_o should be equal to phi_e_i" severity error; end if; if (abs(signed(phi_e_i) - signed(old_phi_e_s)) >= to_integer(unsigned(new_thresh_s))) then sel_s <= '1'; elsif (abs(signed(phi_e_i) - signed(old_phi_e_s)) < to_integer(unsigned(new_thresh_s))) then sel_s <= '0'; end if; else sel_s <= '0'; old_phi_e_s <= (others => '0'); assert phi_e_gr_o = "000000000000000000000000000000000000" report " Output not set to default value when enable_i= 0" severity error; end if; end if; end process;
