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Altera_Forum's avatar
Altera_Forum
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9 years ago

Help needed in VHDL Testbench

Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hello,

One basic question regarding the testbench. If we are not given the VHDL source code but only the components of the design and if we are asked to write a testbench code for its verification, should we need to use "port map" declaration. I assume its not, because we don't have any source file components to port map with. But I am not sure. Can anyone tell me if my assumption is correct or not. Thanks in advance