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Altera_Forum's avatar
Altera_Forum
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9 years ago

Help needed in VHDL Testbench

Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Yes, you can (and will need to ) write a port map. But you cannot run the simulation as there is nothing to bind the component to.

A component just tells the compiler about an entity interface.

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What if I need to run the simulation