--- Quote Start ---
std_logic_vector is not meant to represent arithmetic values, the types unsigned and signed are meant to do that.
Unless you are using non-standard VHDL packages (like std_logic_unsigned/signed), if you are using std_logic_vector, then using >< or = will always fail if there is a missmatch in vector length.
Instead of posting just a extract without the libraries for reference, it can be hard to understand the whole picture. Post the whole code so we can see the code in context.
--- Quote End ---
This is the entire testbench code
p_stim: process
begin
wait for 10 ns;
reset_n_i <= '1';
wait for 15 ns;
enable_i <= '1';
fmcw_trig_i <= '1';
fmcw_bw_i <= "000000000000111000000000";
fstep_i <= "0011100000";
wait for 500 ns;
fmcw_bw_i <= "001111111111111111111111"; -- 4194303
fstep_i <= "0011111111"; -- 255
wait for 1 ms;
fmcw_bw_i <= "011111111111111111111111"; -- 8388607
fstep_i <= "0111111111"; -- 511
wait for 1 ms;
fmcw_bw_i <= "111111111111111111111110"; -- 16777215
fstep_i <= "1111111110"; -- 1023
wait for 10 ms;
reset_n_i <= '0';
wait for 1 ms;
reset_n_i <= '1';
wait for 1 ms;
enable_i <= '0';
fmcw_trig_i <= '0';
wait for 1 ms;
enable_i <= '1';
fmcw_trig_i <= '1';
wait for 1 ms;
assert false report "end of the simulation" severity failure;
end process;
delayed_rst_s <= reset_n_i after 1 ns;
p_check_bw_rst: process(delayed_rst_s, clk_128meg_i)
begin
if (delayed_rst_s = '0') then
assert fmcw_ramp_o = "000000000000000000000000" report "output not set to default value when reset_n_i=0" severity error;
elsif (clk_128meg_i'event and clk_128meg_i = '0') then
if (enable_i= '1' and fmcw_trig_i = '1') then
assert fmcw_ramp_o < std_logic_vector(unsigned(fmcw_bw_i) + unsigned(fstep_i)) report "output value is larger than fmcw_bw_i" severity error;
else
assert fmcw_ramp_o = "000000000000000000000000" report "Output not set to default value when enable_i and fmcw_trig_i=0" severity error;
end if;
end if;
end process;
p_check_step: process(delayed_rst_s, clk_128meg_i)
begin
if (delayed_rst_s = '0') then
dir_s <= '0';
old_fmcw_ramp_s <= (others => '0');
elsif (clk_128meg_i'event and clk_128meg_i = '0') then
if (enable_i = '1' and fmcw_trig_i = '1') then
if( dir_s = '1') then
assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) - unsigned(fstep_i)) report " wrong output: subtraction should take place" severity error;
else
assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) + unsigned(fstep_i)) report " wrong output: addition should take place" severity error;
end if;
if (to_integer(unsigned(fmcw_ramp_o)) > to_integer(unsigned(fmcw_bw_i) - unsigned(fstep_i)))then
dir_s <= '1';
elsif (to_integer(unsigned(fmcw_ramp_o)) <= to_integer(unsigned(fstep_i))) then
dir_s <= '0';
end if;
old_fmcw_ramp_s <= fmcw_ramp_o;
else
dir_s <= '0';
old_fmcw_ramp_s <= (others => '0');
end if;
end if;
end process;
Now I have another problem. My code is not working for the input 16777215. its overflowing and i don't need to do that. Please help me
Honored Contributor
