Help needed in VHDL Testbench

Hello,

I needed to design a glitch rejection module in VHDL and I have written the testbench accordingly only. I don't have the source module but I have the design which is as follows:

http://www.alteraforum.com/forum/attachment.php?attachmentid=12702&stc=1 .

Thetestbench is as follows:

stim_proc:process
  
  begin        
      
    wait for 10 ns;    
    reset_n_i <= '1';
    wait for 15 ns;
    enable_i <= '1';
    phi_e_i <= "101010101111010101101010101101010101"; 
    thresh_i <= "11111111";
    
    wait for 100 ns;
    phi_e_i <= "111010101101010101010101010101010101";
    thresh_i <= "00010110";
    wait for 1 ms;
    reset_n_i <= '0';
  
    wait for 1 ms;
    reset_n_i <= '1';
    wait for 1 ms;
    enable_i <= '0';
    wait for 1 ms;
    enable_i <= '1';
    wait for 1 ms;
    assert False report "End simulation!" severity Failure;
  end process;
  delay_rst_s <= reset_n_i after 1 ns;
  p_check_outp: process(delay_rst_s, clk_128meg_i)
  begin
    if (delay_rst_s = '0') then
      sel_s <= '0';
      old_phi_e_s <= (others => '0');
      assert phi_e_gr_o = "000000000000000000000000000000000000" report "Output not set to default value when reset_n_i= 0" severity error;
    elsif (clk_128meg_i'event and clk_128meg_i = '0')then
      if (enable_i = '1') then
        old_phi_e_s <= phi_e_i; 
        new_thresh_s <= std_logic_vector("0000000000000000000000000000" & thresh_i);
        if (sel_s = '1') then
          assert phi_e_gr_o = old_phi_e_s report "Wrong output: phi_e_gr_o should be equal to old phi_e_i" severity error;
        elsif (sel_s = '0') then
          assert phi_e_gr_o = phi_e_i report "Wrong output: phi_e_gr_o should be equal to phi_e_i" severity error; 
        end if;
        if (abs(signed(phi_e_i) - signed(old_phi_e_s)) >= to_integer(unsigned(new_thresh_s))) then
          sel_s <= '1';
        elsif (abs(signed(phi_e_i) - signed(old_phi_e_s)) < to_integer(unsigned(new_thresh_s))) then
          sel_s <= '0';
        end if;
      
      else
         sel_s <= '0';
         old_phi_e_s <= (others => '0');
         assert phi_e_gr_o = "000000000000000000000000000000000000" report " Output not set to default value when enable_i= 0" severity error;
      end if;
    end if;
  end process;

First, old_phi_e_s should be updated with the phi_e_i only in the rising edge. I don't know how to do this??

What I need to do is , I need to check for the condition if (abs(signed(phi_e_i) - signed(old_phi_e_s)) >= to_integer(unsigned(new_thresh_s))) then, phi_e_gr_o = old_phi_e_s , else phi_e_gr_o = phi_e_i. But it is not doing so. I am getting the errors "Wrong output: phi_e_gr_o should be equal to old phi_e_i" and "Wrong output: phi_e_gr_o should be equal to phi_e_i". Please help me to solve this issue. Thanks in advance.