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Altera_Forum
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9 years ago

Help needed in VHDL Testbench

Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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I'm sorry, yes, I have misspelled it, I have changed fmcw_bw_i to 111111.... but still there is overflowing. Please help me out

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and 1023 should be "111111111"

addition/subtraction output must be 1 bit more than widest input