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bhong1's avatar
bhong1
Icon for New Contributor rankNew Contributor
6 years ago

Help. I don't know where it goes wrong and doesn't work. Simulation does not work.

module dfftest(

input wire in1;

input wire in2;

output wire out1;

wire SYNTHESIZED_WIRE_7;

wire SYNTHESIZED_WIRE_8;

wire SYNTHESIZED_WIRE_4;

assign SYNTHESIZED_WIRE_7 = 1;

assign SYNTHESIZED_WIRE_8 = 1;

dff2_0 b2v_inst(

.CLK(in2),

.D(in1),

.PRN(SYNTHESIZED_WIRE_7),

.CLRN(SYNTHESIZED_WIRE_7),

.Q(SYNTHESIZED_WIRE_4)

);

jkff2_1 b2v_inst2(

.K(SYNTHESIZED_WIRE_8),

.CLRN(SYNTHESIZED_WIRE_8),

.CLK(SYNTHESIZED_WIRE_4),

.PRN(SYNTHESIZED_WIRE_8),

.J(SYNTHESIZED_WIRE_8),

.Q(out1));

endmodule

module dff2_0(CLK,D,PRN,CLRN,Q);

/* synthesis black_box */

input CLK;

input D;

input PRN;

input CLRN;

output Q;

endmodule

module jkff2_1(K,CLRN,CLK,PRN,J,Q);

/* synthesis black_box */

input K;

input CLRN;

input CLK;

input PRN;

input J;

output Q;

endmodule​

7 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    I'm not sure what you're trying to do here. There's no functional logic in this design. What error(s) are you getting and what are you expecting?

    #iwork4intel

    • bhong1's avatar
      bhong1
      Icon for New Contributor rankNew Contributor
      6 years ago

      ​hello.

      d flipflop test result

      It works normally with block diagram.

      It does not work as a verilog-hdl file. d f / f is maxplus dff2.

      sofware is quatus prime 19.1 and verilog is an auto-converted file.

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    Hi Bongjo,

    May I know following info:

    1. What type of Quartus Prime you are suing? Pro,Std,Lite?
    2. What kind of error(s) you get and expectation for your design? Is is fail to compile or cannot simulate etc

    Thanks,

    Regards

  • bhong1's avatar
    bhong1
    Icon for New Contributor rankNew Contributor
    6 years ago

    ​Hi.

    Type is Lite Quartus Prime

    If there is a verilog file, there is no error. D FlipFlop JK There is no output from FlipFlop.

    If you simulate using dff2 and jkff2 of MaxplusII Lib, the output does not appear.

    All other logics of MAXV 5M570 operate normally, but only Dff2 jkff2 of MAXPLUSII does not operate normally.

    I think this is a bug from Quartus Compiler.

    thanks you.

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    Hi Bongjo,

    Could you provide the design file and let me replicate the issue on my side first. Attach the file here in zip file.

    Thanks,

    Regards

    • bhong1's avatar
      bhong1
      Icon for New Contributor rankNew Contributor
      6 years ago
      Hello I attached Project Files. Thanks