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bhong1's avatar
bhong1
Icon for New Contributor rankNew Contributor
6 years ago

Help. I don't know where it goes wrong and doesn't work. Simulation does not work.

module dfftest( input wire in1; input wire in2; output wire out1; wire SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_4; assign SYNTHESIZED_WIRE_7 = 1; assign SYNTHESIZED_...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

I'm not sure what you're trying to do here. There's no functional logic in this design. What error(s) are you getting and what are you expecting?

#iwork4intel

  • bhong1's avatar
    bhong1
    Icon for New Contributor rankNew Contributor
    6 years ago

    ​hello.

    d flipflop test result

    It works normally with block diagram.

    It does not work as a verilog-hdl file. d f / f is maxplus dff2.

    sofware is quatus prime 19.1 and verilog is an auto-converted file.