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bhong1's avatar
bhong1
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6 years ago

Help. I don't know where it goes wrong and doesn't work. Simulation does not work.

module dfftest( input wire in1; input wire in2; output wire out1; wire SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_4; assign SYNTHESIZED_WIRE_7 = 1; assign SYNTHESIZED_...
bhong1's avatar
bhong1
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6 years ago

​Hi.

Type is Lite Quartus Prime

If there is a verilog file, there is no error. D FlipFlop JK There is no output from FlipFlop.

If you simulate using dff2 and jkff2 of MaxplusII Lib, the output does not appear.

All other logics of MAXV 5M570 operate normally, but only Dff2 jkff2 of MAXPLUSII does not operate normally.

I think this is a bug from Quartus Compiler.

thanks you.