Forum Discussion

bhong1's avatar
bhong1
Icon for New Contributor rankNew Contributor
6 years ago

Help. I don't know where it goes wrong and doesn't work. Simulation does not work.

module dfftest( input wire in1; input wire in2; output wire out1; wire SYNTHESIZED_WIRE_7; wire SYNTHESIZED_WIRE_8; wire SYNTHESIZED_WIRE_4; assign SYNTHESIZED_WIRE_7 = 1; assign SYNTHESIZED_...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
6 years ago

Hi Bongjo,

May I know following info:

  1. What type of Quartus Prime you are suing? Pro,Std,Lite?
  2. What kind of error(s) you get and expectation for your design? Is is fail to compile or cannot simulate etc

Thanks,

Regards