Honored ContributorHi all,
I am new in verilog and quartus.. I have a module that is successful compile but the logic elements is indicated to be zero used. The register and net inside my module is found to be undefined in vector waveform when i run simulation.... Any idea what's wrong with my code?? mixcolumn_en.v will be my top-level Regards Vinz
Honored ContributorI'm not a Verilog specialist, but I think that you should have at least have your last always block in your top level file to be triggered by a clock edge. I don't know how your code would be synthesized, but it probably won't do what you expect... If Quartus finds out that your outputs never change, it will just optimize the design by removing everything.
Honored ContributorI have tried clock edge in my top level. The problem still exist. I not familiar with hardware language as I use to do software programming. Hence I not sure whether i do it in the right way. But anyway thanks for your advice...
Honored Contributoralways @(N)
begin
data1<=data2;
data2<=data3;
data3<=data4;
data4<=data1;
endIf I understand correctly what you are trying to do, those statements should be in your last always block, triggered by a clock edge.
Honored ContributorHello,
I have met the same problem, trying to implement a CAN IP core, I built a project which contains only the core, the compilation is good but with 0 logic element used... I'm pretty sure about the verilog code (stable version downloaded from OpenCores and modelsim verified). So what kind of problem can lead to this problem, Can anyone help me ? Thanks a lot.Honored ContributorQuartus optimises your component away, most probably because it determined that an empty FPGA would do exactly the same thing that what you described. That is usually the case if the core you inserted doesn't drive any output pins, doesn't depend on any input pin and/or is kept in a constant state (kept in reset, for example, or with no clock input).
