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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help!!! Compilation Successful but zero logic element used!!!

Hi all, I am new in verilog and quartus.. I have a module that is successful compile but the logic elements is indicated to be zero used. The register and net inside my module is found to be un...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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I not familiar with hardware language

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Yes, it's pretty obvious when seeing your code. I guess you'll need a tutorial or textbook.

The below construct makes all datax variables undefined and can already explain, why you don't get any output from the design. N is simply ignored, so the code means to put the four signals in a logic chain. The meaningless construct will be discarded by a design compiler. 

always @(N)
begin
data1<=data2;
data2<=data3;
data3<=data4;
data4<=data1;
end