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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help!!! Compilation Successful but zero logic element used!!!

Hi all, I am new in verilog and quartus.. I have a module that is successful compile but the logic elements is indicated to be zero used. The register and net inside my module is found to be un...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If I understand correctly what you are trying to do, those statements should be in your last always block, triggered by a clock edge.