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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help!!! Compilation Successful but zero logic element used!!!

Hi all, I am new in verilog and quartus.. I have a module that is successful compile but the logic elements is indicated to be zero used. The register and net inside my module is found to be un...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm not a Verilog specialist, but I think that you should have at least have your last always block in your top level file to be triggered by a clock edge. I don't know how your code would be synthesized, but it probably won't do what you expect... If Quartus finds out that your outputs never change, it will just optimize the design by removing everything.