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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help!!! Compilation Successful but zero logic element used!!!

Hi all, I am new in verilog and quartus.. I have a module that is successful compile but the logic elements is indicated to be zero used. The register and net inside my module is found to be un...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hello,

I have met the same problem, trying to implement a CAN IP core, I built a project which contains only the core, the compilation is good but with 0 logic element used... I'm pretty sure about the verilog code (stable version downloaded from OpenCores and modelsim verified).

So what kind of problem can lead to this problem, Can anyone help me ?

Thanks a lot.