Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Gate level Simulation passes but design fails on target borad

Hello,

I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz.

I simulated the design using ModelSim.

My Target hardware consists of stratix II device.

Input stimulus is sine wave of desired frequency.

Inputs coefficients decide the cutoff frequency.

Expected result is attenuation of sine wave at cut-off freq.

Design works fine in RTL as well as Gate level simulation.

1)

However, when programmed on target hardware, it fails completly and has output has no attenuation at lower frequencies (100Hz) and wrong beaviour at higher frequencies.

2)

I see that fast/slow model results in timing analyses show failures linked to my design. It indicated a different (40MHz) clock domain in the from/to section of the report. 40MHz is used for other sections and I don't use 40 Mhz for this piece of design.

-------------------------------------------------------

Please suggest me how to go ahead from gate level simulation to on board running. I am kind of stuck, unable to proceed further.

Is there any settings that i need to check.

Thanks in advance.

Best Regards,

VVP

36 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I am a bit surprised that 40MHz fails speed. There must be something unusual in your clocking scheme.

    With regard 20MHz, remember it will affect your frequency point. If you are reading your sine input from LUT then all frequencies will go by half if sampled at 20MHz (unless your clken rate of 100 KHz is maintained).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I am giving a fixed sine wave of say 100 Hz. Expecting that it gets attenuated to 10% if coefficients corresponding to 100Hz are provided. CLock can be 20 Mhz (for testing) or 40 Mhz (desired) but with fixed clock_enable, which toggles at 500Khz rate.

    However, on board it still does not give better results.

    Please advice.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    After looking back at some of the figures in this post, it seems I assumed sampling freq was 100K but actually you are saying it is 500KHz. Thus the two filters notch point must be moved 5 time higher (100Hz => 500Hz...etc).

    So obviously both my analysis and your friend's point to same response but is in conflict with your expectations of actual frequency. Anyway, it is a not problem, all you need is look at the frequency point that corresponds to 5 times our posted figures.

    The rule is simple: freq out = normalised freq * sampling freq/2.

    normalised freq is 1.0 at half sampling freq.(in matlab functions)

    A good indicator that your filter is wrong is if output is weird provided input freq is a regular sine.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hello,

    i was away for couple of days due to personal reasons.

    Agree to your point.

    I tried something different now.

    I reduced the sampling freq,Fs=125 KHz & then to 31.25 KHz for testing.

    It works (on board) for Fc=100Hz also and the output waveform looks good.

    But when I change the FS=500KHz, it does not work.

    I don't have timing issues (as of now as i changed the clock to 20mhz as i reported to you earlier for sake of testing and to pin-point the issue).

    please advice.

    Best Regards,

    VVP
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi,

    I hope you realise that changing Fs for a given filter will change the response proportionally.

    If your filter is fixed for a response at Fs of 500Ksps to produce a notch at 100Hz, then that notch point will move to 100 *125/500 = 25Hz if Fs is made 125Ksps.

    How do you know your input is at a given freq. If you generate from LUT then the freq will depend on Fs at LUT
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Agreed to ur point.

    I now, can generate freq from signal generator in the board set up.

    In this case I have control over the freq of the input signal.

    I then can give different Fc for a fixed Fs=125khz or 31.25khz of 500khz.

    This is the way i checked the response.