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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I am giving a fixed sine wave of say 100 Hz. Expecting that it gets attenuated to 10% if coefficients corresponding to 100Hz are provided. CLock can be 20 Mhz (for testing) or 40 Mhz (desired) but with fixed clock_enable, which toggles at 500Khz rate.

However, on board it still does not give better results.

Please advice.