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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
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Altera_Forum
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14 years ago

I am a bit surprised that 40MHz fails speed. There must be something unusual in your clocking scheme.

With regard 20MHz, remember it will affect your frequency point. If you are reading your sine input from LUT then all frequencies will go by half if sampled at 20MHz (unless your clken rate of 100 KHz is maintained).