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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hello,

i was away for couple of days due to personal reasons.

Agree to your point.

I tried something different now.

I reduced the sampling freq,Fs=125 KHz & then to 31.25 KHz for testing.

It works (on board) for Fc=100Hz also and the output waveform looks good.

But when I change the FS=500KHz, it does not work.

I don't have timing issues (as of now as i changed the clock to 20mhz as i reported to you earlier for sake of testing and to pin-point the issue).

please advice.

Best Regards,

VVP