Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

For better simulation performance what mode of ALTPLL is recommended?

Hello,

I am working on a FPGA as functional verification engineer. We are using ALTPLL in our simulation and it is currently using more than 60% of simulator resources (altera_mf.v). Do you generally black box ALTPLL during functional verification? or Do you put it in bypass mode? Or you use it in active mode? This is the user's guide of PLL that we are using.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altpll.pdf

I am planning to blackbox PLL for functional simulation. I thought I'd check with you first and see what is the common approach in FPGA simulation regarding PLL.

a) Do folks generally run simulation with PLL model?

b) Do they generally put PLL in bypass mode? And in some occasion like weekend runs, use active pll model?

c) Do they blackbox PLL model?

d) Is there any value to run all the simulation with active PLL model and spending so much of simulation cycle?

any advice is highly appreciated.

Regards,

amir

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    a) no

    b) no

    c) no

    d) no

    I just dont simulate the PLL at all. I just use modelled clocks at the top level. For functional verification, you dont really care what the clock speed is - its the number of clocks thats important. Just do something like this in your testbench:

    always# 5 clk = ~clk;

    and do the same for any other clocks with roughly the correct timing relationships. I chose 100Mhz because it's then easier to measure the number of clocks between two cursors on a wave window.

    I trust the PLL to work.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    The only time you would want to simulate the PLL is if your code manipulates or re-configures it and you want to test that feature. If you just have the PLL set to generate a fixed set of clocks, write some code in your testbench to provide them in place of the PLL simulation.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thx for your input. I understand the point and I plan to use some simple verilog code to create clock. How would I disable the PLL in altera_fm.v file? any specific inputs that I need to tie to 0/1 to disable ALTPLL?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Keep things simple and just don't instantiate the ALTPLL in your simulation model; substitute it wholesale with your generated clocks.