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Altera_Forum
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10 years ago

For better simulation performance what mode of ALTPLL is recommended?

Hello, I am working on a FPGA as functional verification engineer. We are using ALTPLL in our simulation and it is currently using more than 60% of simulator resources (altera_mf.v). Do you ...
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Altera_Forum
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10 years ago

Thx for your input. I understand the point and I plan to use some simple verilog code to create clock. How would I disable the PLL in altera_fm.v file? any specific inputs that I need to tie to 0/1 to disable ALTPLL?