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Altera_Forum
Honored Contributor
Honored ContributorFor better simulation performance what mode of ALTPLL is recommended?
Hello, I am working on a FPGA as functional verification engineer. We are using ALTPLL in our simulation and it is currently using more than 60% of simulator resources (altera_mf.v). Do you ...
Altera_ForumHonored Contributor
Honored ContributorThe only time you would want to simulate the PLL is if your code manipulates or re-configures it and you want to test that feature. If you just have the PLL set to generate a fixed set of clocks, write some code in your testbench to provide them in place of the PLL simulation.
