For better simulation performance what mode of ALTPLL is recommended?

a) no

b) no

c) no

d) no

I just dont simulate the PLL at all. I just use modelled clocks at the top level. For functional verification, you dont really care what the clock speed is - its the number of clocks thats important. Just do something like this in your testbench:

always# 5 clk = ~clk;

and do the same for any other clocks with roughly the correct timing relationships. I chose 100Mhz because it's then easier to measure the number of clocks between two cursors on a wave window.

I trust the PLL to work.