FIFO Works fine on EDAPlayground but not Quartus

//////////////////////////////////////////////////////////////////////
//================================================================
// FIFO test in an array specfic for HiDS
// set up for Dual clocks
//      one to Write
//      one to Read
// also will need to have 2 data busses
//      Data IN
//      Data OUT
// Extras
//      nReset -- CLR on LO
//      Empty -- HI indicates empty
module DFIFO_array(D_Out, Empty, D_In, wrclk, rdclk, nrst);
  
  output  D_Out;
//output  D_Out;
  output Empty;
  reg  D_Out;
//reg  D_Out;
      
  input  D_In;
//input  D_In;
  
  input wrclk;
  input rdclk;
  input nrst;
  
  // 
  // DFIFO for 64 Channel SAM 41 x 32
  // EFIFO for 64 Channel SAM 10 x 64
  parameter WIDE = 41;
  parameter DEEP = 32;
  
  // this should give us a FIFO of 41 bits Wide by 32 words deep
  // 9-bit counter in MSB bits 32:41
  // 32-bit channel representation in 0:31 
  //
  // 
  reg  addr;
//reg  addr;
  reg  w_addr;
  reg  r_addr;
  
  always @ (posedge wrclk)
    begin
      addr <= D_In;
      w_addr <= w_addr + 1;
    end
  
  always @ (posedge rdclk)
    begin
      r_addr <= r_addr + 1;
      D_Out <= addr;
    end
  
  always @ (nrst)
    begin
      if (!nrst)
        begin
          w_addr <= 0;
          r_addr <= 0;
        end
    end
  
  assign Empty = (w_addr == r_addr);
  
endmodule
/////////////////////////////////////////////////////////////

You need reset outside (before) clock edge

This is incorrect semantics for implementing a synchronously clocked register with an asynchronous reset:

  always @ (posedge rdclk)
    begin
      r_addr <= r_addr + 1;
      D_Out <= addr;
    end
  
  always @ (nrst)
    begin
      if (!nrst)
        begin
          r_addr <= 0;
        end
    end

  always @ (posedge rdclk or negedge nrst)
    begin
      if (!nrst)
           begin
           r_addr <= 0;
           end
      else
           begin
           r_addr <= r_addr + 1;
           D_Out <= addr;
           end
    end