FIFO Works fine on EDAPlayground but not Quartus

This is incorrect semantics for implementing a synchronously clocked register with an asynchronous reset:

  always @ (posedge rdclk)
    begin
      r_addr <= r_addr + 1;
      D_Out <= addr;
    end
  
  always @ (nrst)
    begin
      if (!nrst)
        begin
          r_addr <= 0;
        end
    end

  always @ (posedge rdclk or negedge nrst)
    begin
      if (!nrst)
           begin
           r_addr <= 0;
           end
      else
           begin
           r_addr <= r_addr + 1;
           D_Out <= addr;
           end
    end