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Altera_Forum's avatar
Altera_Forum
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8 years ago

FIFO Works fine on EDAPlayground but not Quartus

All, The following code works fine and as expected on EDAPlayground, but Quartus has an issue with it. I get the ERROR 10028 Can't resolve multiple constant drivers for nets w_addr and r_addr. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

This is incorrect semantics for implementing a synchronously clocked register with an asynchronous reset: 


  always @ (posedge rdclk)
    begin
      r_addr <= r_addr + 1;
      D_Out <= addr;
    end
  
  always @ (nrst)
    begin
      if (!nrst)
        begin
          r_addr <= 0;
        end
    end

You need to rewrite the each register as a single always block: 


  always @ (posedge rdclk or negedge nrst)
    begin
      if (!nrst)
           begin
           r_addr <= 0;
           end
      else
           begin
           r_addr <= r_addr + 1;
           D_Out <= addr;
           end
    end