Honored ContributorHi all,
When I performed a full compilation on my vhdl project, I have the following errors: 1- failed to route the following signal 2- cant fit design in device Please help me out ~
Honored ContributorThe errors are rather clear: your design is too big for that device.
I believe you have already check the right device is selected, right? Then, are you sure your VHDL project should actually fit into it? Maybe you badly instantiated some components and the design generates a lot of extra logic you actually don't need. Or maybe you defined some memory components with a width not matching the fpga memory blocks width and this unexpectedly waste resources. RegardsHonored ContributorNo routes are a little different than general no-fits. (I think of no-fits as the ones where the design uses more than 100% of the resources). What's the average and peak routing utilization? Some things that can cause this:
- High Logic Utilization but still below 100%. There's kind of a peak where a design might not use 100% but is unroutable. - Low fitter effort. For example if you set the fitter effort level to Fast Fit, that can cause a no-fit. - Large hold requirements(this is usually a mistake in multicycle constraints, where users enter multicycle -setup constraints but no corresponding -hold requirements.) In the fitter report look for "Estimated Delays added for hold requirement" (It's something like that.)Honored ContributorThere is one thing I would like to mention which is my project actually took more than a day to complete just analysis and synthesizing. It took up 99014 LEs. So is the long analysis and synthesizing normal?
Honored ContributorHonored ContributorIm using Cyclone III EP3C120F780I7.
under what circumstances the code will be hard to synthesize? will that lead to failure in routing the signals?Honored ContributorHonored ContributorHonored ContributorLong synthesis times and a no-route are technically different. Once it's through synthesis, it's a structuryal netlist that gets passed to the fitter. That being said, a day long synthesis is REALLY long. I've never seen anything close to that. Is 99K LEs about what you'd expect? Perhaps you're running on a slow machine?
THe times I've seen synthesis run off into the weeds is when designs are purely abstract, and the user expects things to get synthesized out. For example, I saw one that was only 50K LUTs, but when I started synthesized sub-modules by themselves(so reductions wouldn't occur) small hierarchies blew up to hundreds of thousands of LUTs. So basically synthesis was creating over a million LUTs and then finding reductions to bring it down to ~50K. That is very uncommon, and not what synthesis is really designed to do.Honored ContributorIm running on AMD Athlon 64x2 Dual core processor 5600+ 2.8GHz. Though it maybe a fast machine, i do think a day long is really way too long. Im thinking perhaps the synthesizer is trying to perform reduction like you mentioned. How can I avoid it from doing so?
and I still havent solve the "failed to route the signals" problemHonored ContributorSynthesizing 99K LEs should take an hour or two. If something was difficult, maybe double that. There is no way it should take a day. If it's due to reductions, you want it to do that because the design would most likely be many times larger(if that's the problem). As recommended, start making sub-projects of smaller hierarchies and benchmark those(synthesis times, how large they are, etc.) and see if there is a problem area. If you can send the design, might be worth a Service Request with Altera.
