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Altera_Forum's avatar
Altera_Forum
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14 years ago

Failed to route the following signal

Hi all, When I performed a full compilation on my vhdl project, I have the following errors: 1- failed to route the following signal 2- cant fit design in device Please help me ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Hi,

Long elaboration and synthesis runs could have a lot of reasons. Failure in routing could be caused by different reasons. Which design language are you using ? I would try to

setup test projects for each main block of your toplevel, in order to find out which block

causes the long runs.

Kind regards

GPK

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thanks alot! i would really appreciate your help!

im using VHDL