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Altera_Forum's avatar
Altera_Forum
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14 years ago

Failed to route the following signal

Hi all, When I performed a full compilation on my vhdl project, I have the following errors: 1- failed to route the following signal 2- cant fit design in device Please help me ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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There is one thing I would like to mention which is my project actually took more than a day to complete just analysis and synthesizing. It took up 99014 LEs. So is the long analysis and synthesizing normal?

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Hi,

looks to me that at least parts of the design are not easy to synthesize. Any timing constrains set ? Which FPGA device are you using ?

Kind regards

GPK