Failed to compile project with altlvds with external pll on Cyclone V, Quartus Standard 18.1

Hi,

Could anybody give me advise what to do or try?

I compile a project with 27 lvds lines running at 384MHz sampling frequency. There is 3 input clocks for each group of 9 lines separately. The reference clocks are connected to CLK[1,2,3] pins.

If I connect LVDS lines only to pins in bank 3A, 3B, 4A and 4B all compiles fine but if i connect one pin to bank 5A (PIN_Y17 and PIN_Y18) compilation fails. PCB board is already produced and some LVDS lines are connected to bank 5A. The compilation error message is the following:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (89, 4) to (89, 9), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): i_afe_d[6]
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info (175015): The I/O pad i_afe_d[6] is constrained to the location PIN_Y17 due to: User Location Constraints (PIN_Y17)
Info (14709): The constrained I/O pad is contained within this pin
Error (175010): Location failed detailed legality checks (1 location affected)
Info (175029): pin containing PIN_Y17

I also tried to compile the project with the newer Quartus version 21.1 but the newer version crashes after a similar compilation error message and I cannot explore the error messages. I use 18.1 version as the previous version of firmware for a similar board was compiled in 18.1 and we did some workaround for HPS and so on, so i do not want to switch to a newer version in general.