Failed to compile project with altlvds with external pll on Cyclone V, Quartus Standard 18.1

Hi,

Thank you for reaching out.

The device is 5CSXFC6C6U23I7.

In a meanwhile I did some more testing. and figured out that I cannot rout pll signals for lvds_serdes to 5A from the same pll as for 3A, 3B, 4A and 4B.