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AntonKu
New Contributor
New ContributorFailed to compile project with altlvds with external pll on Cyclone V, Quartus Standard 18.1
Hi, Could anybody give me advise what to do or try? I compile a project with 27 lvds lines running at 384MHz sampling frequency. There is 3 input clocks for each group of 9 lines separately. The re...
AntonKuNew Contributor
New ContributorHi,
Thank you for reaching out.
The device is 5CSXFC6C6U23I7.
In a meanwhile I did some more testing. and figured out that I cannot rout pll signals for lvds_serdes to 5A from the same pll as for 3A, 3B, 4A and 4B.
